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THE CONTEXT OF PARALLEL PROCESSING The field of digital computer architecture has grown explosively in the past two decades. Through a steady stream of experimental research, tool-building efforts, and theoretical studies, the design of an instruction-set architecture, once considered an art, has been transformed into one of the most quantitative branches of computer technology. At the same time, better understanding of various forms of concurrency, from standard pipelining to massive parallelism, and invention of architectural structures to support a reasonably efficient and user-friendly programming model for such systems, has allowed hardware performance to continue its exponential growth. This trend is expected to continue in the near future. This explosive growth, linked with the expectation that performance will continue its exponential rise with each new generation of hardware and that (in stark contrast to software) computer hardware will function correctly as soon as it comes off the assembly line, has its down side. It has led to unprecedented hardware complexity and almost intolerable dev- opment costs. The challenge facing current and future computer designers is to institute simplicity where we now have complexity; to use fundamental theories being developed in this area to gain performance and ease-of-use benefits from simpler circuits; to understand the interplay between technological capabilities and limitations, on the one hand, and design decisions based on user and application requirements on the other.
It is our pleasure to welcome you to the proceedings of the 13th International C- puter Society of Iran Computer Conference (CSICC-2008). The conference has been held annually since 1995, except for 1998, when it transitioned from a year-end to first-quarter schedule. It has been moving in the direction of greater selectivity (see Fig.1) and broader international participation. Holding it in Kish Island this year represents an effort to further facilitate and encourage international contributions. We feel privileged to participate in further advancing this strong technical tradition. 60 50 40 30 20 10 0 Dec 23-26 Dec 23-25 Dec 23-25 Jan 26-28 Mar 8-10 Feb 21-23 Feb 28-30 Feb 23-26 Feb 16-19 Feb 15-18 Jan 24-26 Feb 20-22 Mar 9-11 1995 1996 1997 Iran 1999 2000 2001 U of 2002 Iran 2003 2004 2005 Iran 2006 IPM, 2007 2008 Sharif U Amirkabir U of Sharif U Shahid Isfahan, Telecom Ferdowsi Sharif U Telecom Tehran Shahid Sharif U of Tech, U of Tech, Sci/Tech, of Tech, Beheshti Isfahan Res. U, of Tech, Res. Beheshti of Tech, Tehran Tehran Tehran Tehran U, Tehran Center Mashhad Tehran Center U, Tehran Kish Island Dates, Year, Venue
THE CONTEXT OF PARALLEL PROCESSING The field of digital computer architecture has grown explosively in the past two decades. Through a steady stream of experimental research, tool-building efforts, and theoretical studies, the design of an instruction-set architecture, once considered an art, has been transformed into one of the most quantitative branches of computer technology. At the same time, better understanding of various forms of concurrency, from standard pipelining to massive parallelism, and invention of architectural structures to support a reasonably efficient and user-friendly programming model for such systems, has allowed hardware performance to continue its exponential growth. This trend is expected to continue in the near future. This explosive growth, linked with the expectation that performance will continue its exponential rise with each new generation of hardware and that (in stark contrast to software) computer hardware will function correctly as soon as it comes off the assembly line, has its down side. It has led to unprecedented hardware complexity and almost intolerable dev- opment costs. The challenge facing current and future computer designers is to institute simplicity where we now have complexity; to use fundamental theories being developed in this area to gain performance and ease-of-use benefits from simpler circuits; to understand the interplay between technological capabilities and limitations, on the one hand, and design decisions based on user and application requirements on the other.
Ideal for graduate and senior undergraduate courses in computer
arithmetic and advanced digital design, Computer Arithmetic:
Algorithms and Hardware Designs, Second Edition, provides a
balanced, comprehensive treatment of computer arithmetic. It covers
topics in arithmetic unit design and circuit implementation that
complement the architectural and algorithmic speedup techniques
used in high-performance computer architecture and parallel
processing. Using a unified and consistent framework, the text
begins with number representation and proceeds through basic
arithmetic operations, floating-point arithmetic, and function
evaluation methods. Later chapters cover broad design and
implementation topics-including techniques for high-throughput,
low-power, fault-tolerant, and reconfigurable arithmetic. An
appendix provides a historical view of the field and speculates on
its future.
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